The continual scaling of semiconductor components is generally also accompanied by an increase in the aspect ratio (depth/width) of the trench and relief structures therein, which are formed on substrates. At a structural level of ≦100 nm, aperture angles of around 0.1° are achieved in some instances. The small aperture angles make it increasingly difficult to fill these extremely steep profiles. Although highly conformal deposition methods (almost 100%) have been specially developed for a wide variety of conducting or insulating filling layers, extremely small production dictated profile fluctuations result in the occurrence of non ideally closed closing joints (voids) along the centre axis of such field trench and relief structures.
The particular disadvantages of such voids are to be seen in the fact that they reduce the geometrical cross section of conductive fillings in an uncontrolled manner and thereby increase the electrical resistance thereof or adversely affect other parameters. Thus, storage capacitors for DRAM cells are fabricated for example by deep trench etching, dielectric coating of the trench walls and subsequent filling of the trench with a conductive material. Voids in this conductive filling increase the resistance thereof in an uncontrolled manner.
For the frequently occurring case in which fillings of trenches or reliefs have to be superficially planarized or (partially) etched back (recess etching) for functional reasons, voids in the filling lead, depending on their size, to local fluctuations in the planarization or recess etching rate. That leads to uncontrollable fluctuations for the depth position and the profile of the planarized or recess areas. Generally, the void region is significantly enlarged in terms of width and depth. Under certain circumstances, that affects the further processing and the parameters of these arrangements by a non-reproducible (v shaped) relief of the planarization or recess surface of the primary filling being reproduced in a subsequent layer deposition. If the subsequent layer is then to be removed again by means of anisotropic RIE etching (reactive ion etching) on the recess surface, that is not completely successful. The cause of this is that the layer material of the subsequent layer has been deposited deep into the void region. That then leads to electrical short circuits (given insulated filling layer and conductive subsequent layer) or to interruptions in the current path (given conductive filling layer and insulating subsequent layer) and may additionally act as a particle and contamination source during the further processing.
The production of these voids has been avoided hitherto by means of a sufficiently v-shaped profile of the trench or relief structures. During a highly conformal deposition of the filling layer, the latter thereby accretes from bottom to top in void free fashion at its seam location. The further scaling of the structures means that it is no longer possible to furnish the area requirement for the wall inclination of the trench or relief structures. The reproducible setting of very steep sidewalls of the trench or relief structures is extremely problematic, which is why this method is increasingly failing to work.
Another practically proven possibility for subsequently closing the void independently of the profile of the trench or relief structures consists in the use of an additional thin conformal deposition (divot fill) comprising the same material type (conductive or insulating) as the primary filling layer and subsequent (wet chemical) removal of the divot fill layer deposited on the substrate surface and on the sidewalls of the relief structure.
In this case, it is disadvantageous that the recess etchings effected before the divot fill are not improved. Primarily, however, the process window for the recess etching of the divot fill is very small. Either residues subsequently remain on the substrate surface and the walls of the trench or relief structures, or the void is completely or at least partially opened again.
U.S. Pat. No. 6,359,300 discloses a deep trench capacitor in a wafer with void free filling. The trench capacitor comprises a substrate, a trench formed in the substrate and a conductive filling material which completely fills the trench and comprises doped germanium or a silicon germanium alloy.
In order to achieve a void free filling, the conductive doped germanium or the silicon germanium alloy is deposited in the trench and a filling layer is produced on the substrate. Afterwards, the wafer is heated until the filling layer melts and flows completely into the trench.
Such a method is not practicable for polysilicon, SiO2 or metal filling layers owing to the high temperatures required.
U.S. Pat. No. 4,666,737 describes the metallization of deep vias in an insulating layer. In a first deposition process, the trench and relief structures are coated with a first primary conformal layer of tungsten. Then, a plasma-chemical v-etching reaching down to a predetermined depth of the trench structure is performed in order to produce a v-profile. A second primary conformal filling layer of aluminum is then deposited until the trench and relief structure is completely continuous. However, this method is not suitable for filling particularly deep trench and relief structures.
A similar but more complex method is disclosed by PATENT ABSTRACTS OF JAPAN vol. 1995, No. 09, 31 Oct. 1995 (1995-10-31) and Japanese publication 07-161703 A.
U.S. Pat. No. 5,451,809 has disclosed a method for producing trench capacitors in which the trench is filled with a conductive silicon by multiple coating alternating with etching-back.